A SysML and CLEAN-based methodology for digital circuits design

Due to the ever complexity of digital systems, there is a noticeable need for more abstract and structural mechanisms as well as design methodologies that systematically and formally derive low level concrete designs from high level abstract ones. To this aim, we present a methodological design approach that automatically generates a functional HDL code from SysML diagrams modeling hardware designs. The generated HDL code is both reliable and executable. While the first feature remains crucial for low level design refinements, the second one enables evaluating design performances at early stages. A case study involving the functional implementation of an ALU (Arithmetic Logic Unit) through Clean code generated from high level SysML diagrams is given, to practically show the potential features of the proposed approach. Keywords— Digital circuits design, SysML, Clean, Functional specification, Modeling, Simulation.